1. Field of the Invention
The present invention relates to a device and method for controlling a memory, and more particularly, a device and method for controlling a memory in a digital video (or versatile) disk reproducing device.
2. Description of the Related Art
A digital video disk, as a disk medium for a digital moving picture, is an inexpensive multimedia memory device capable of recording high quality video/audio data. Such a digital video disk can store over 2 hour's worth of an MPEG2 (Moving Picture Experts Group 2) digital image.
Referring to FIG. 1, there is illustrated a general digital video disk (DVD) reproducing device, in which a disk motor 160 rotates a disk 100 at a constant speed, and an optical pickup 140, with a head 120, reads a digital image on the disk 100 and converts the digital image into an analog high frequency (RF) signal. The converted analog signal compensates the feature of RF frequency input through a radio frequency equalizer RF EQ and is reshaped into a pulse, and a to generate ESM (Eight-to-Sixteen Demodulation) data of a data stream via an ESM slicer (not shown). The ESM data is applied to a digital phase locked loop (hereinafter, referred to as "PLL") 300 a system decoder 200 wherein the PLL 300 generates a first clock phase locked with a signal reproduces from the disk 100, thereby generating a clock PLCK capable of reading the ESM data in the system decoder 200. The digital PLL 300 includes a phase comparator, a voltage controlled oscillator and a frequency demultiplier, (all not shown) to generate the first clock phase locked with the signal reproduced from the disk 100 to generate the clock PLCK. A disk drive controller 400 controls a constant linear velocity of the disk revolution and other disk operations according to a frame synchronous signal Sf supplied from a synchronization detector (not shown) of the system decoder 200, in the light of a frequency servo and a phase servo. First and second memories 330 and 280 are a 128 Kb SRAM (Static Random Access Memory) and a 4 Mb RAM, respectively. The former is used for an error correction, while the latter is used for a VBR (Variable Bit Rate) buffer or a data buffer. The system decoder 200 demodulates the data read out from the disk 100 into the original state. The demodulated data is stored in the first memory 330 and read out by a block unit to correct errors at the system decoder 200. The error corrected data is stored again into the first memory 330. Further, the system decoder 200 descrambles the data read out from the first memory 330, to store the descrambled data into the second memory 280. The descrambled data is again read out from the second memory 280 and supplied to a demultiplexer 610 through the system decoder 200. The demultiplexer 610, as a data parser, provides an AC3/MPEG audio decoder 630 with an audio signal and an MPEG2 video decoder 620 with a video signal, respectively. A microcomputer 500 controls an overall operation of the optical disk reproducing system, and generates a transfer control signal in response to a data transfer start signal from the audio decoder 630 or the video decoder 620. The audio and video data demodulated respectively at the audio decoder 630 and the video decoder 620 are provided to a speaker 970 and a monitor 960 through a digital-to-analog converter 800 and an NTSC (or PAL) encoder 700, respectively. A ROM (Read Only Memory) decoder 950 is commonly prepared in a host computer (e.g., a personal computer) and operates according to a control of the host computer. The ROM decoder 950 transfers data generated from the system decoder 200 to the host computer based on a predetermined interfacing method.
Referring to FIG. 2, there is shown a detailed diagram of a section of the system decoder 200 related to controlling the first and second memories 330 and 280. Referring to FIGS. 3A and 3B, there are shown detailed diagrams of the first and second memories 330 and 280, respectively.
The first memory 330, as an error correction buffer, includes three regions ESM.sub.-- wr, PI/PO.sub.-- rd/wr, and Transfer, as shown in FIG. 3A. The region ESM.sub.-- wr buffers 8-14 modulation data of the data stream ESM generated from the disk 100. The region PI/PO.sub.-- rd/wr performs a PI/PO error correction with respect to an error correction block that has been buffered. The region Transfer is to transfer the error corrected data to the second memory 280. The second memory, as a VBR buffer, includes a region for buffering the error corrected data and another region for transferring data in accordance with a request from the audio and video decoders 620 and 630 or the ROM decoder 950, as shown in FIG. 3B. Further, a reference numeral (1) represents an absolute value obtained by subtracting an address for buffering the error corrected data into the memory from an address for transferring data to the audio and video decoders 620 and 630 or the ROM decoder 950. A reference numeral (2) represents an absolute value obtained by subtracting an address for transferring data to the audio and video decoders 620 and 630 or the ROM decoder 950 from an address for buffering the error corrected data into the memory. Referring to FIG. 3B, for example, suppose that the whole memory size is S, the domain of "data buffering" is B, and the domain "data transferring" is T. If B&lt;T, (1)=S-(T-B) and (2)=T-B. However, if B&gt;T,(1)=B-T and (2)=S-(B-T).
The system decoder 200 includes a demodulator 250, an ECC (Error Correction Circuit) 230, an ECC memory controller 503, a VBR memory controller 506, and a descrambler 240. The demodulator 250 demodulates the input data stream ESM by the symbol unit of predetermined bit numbers. On the other words, the demodulator 250 applies the data stream ESM to a 32-bit shift register (not shown). Lower (or upper) 16 bits out of the 32-bit output from the 32-bit shift register are transferred to a 16-8 demodulator (not shown). The 32-bit shift register and the 16-8 demodulator are typically provided in the demodulator 250. The 16-8 demodulator converts the 16-bit data input into 8-bit data which constitutes the symbol. This operation should be performed, since the data has undergone the 8-16 modulation when being written on the disk 100.
The ECC (Error Correction Circuit) memory controller 503 controls an access to the first memory 330, in order to correct an error with respect to the demodulated data. The ECC 230 corrects an error in the row and column directions with respect to a predetermined error correction block including the data read from disks in a DVD (Digital Video Disk) system. It should be noted that in the application, the data are of (182, 172, 11) in row and (208, 192, 17) in column, respectively. Namely, lengths of the codeword are respectively 182 in row and 208 in column, lengths of main data excluding parity are respectively 172 in row and 192 in column, and intervals between the codewords are respectively 11 in row and 17 in column. In order to perform such error correction, the first memory 330 receives ID (Identification) data and main data generated from the demodulator 250 and stores those data by the block unit, so as to form the error correction block. The error correction block includes data for 16 sectors. Further, the first memory 330 also buffers the data while the error corrections are executed in the row and column directions, and stores the error corrected data.
A VBR memory controller 506 controls an access to the second memory 280 in order to VBR-buffer the error corrected data. Namely, the VBR memory controller 506 allows the second memory 280 to buffer the descrambled DVD data and transfers the buffered data to the audio and video decoders 620 and 630 according to the data transfer control signal generated from the microcomputer 500.
A descrambler 240 reads and descrambles the main data which has been scrambled prior to being written on the disk 100, to restore to the original data. The main data is 2 Kbyte in size.
A system clock generator 900 generates a clock signal used by the disk drive controller 400.
As can be appreciated from the above descriptions, the prior art DVD reproducing device includes the error correction memory and the VBR or data buffering memory separately. Accordingly, the memory controllers should be prepared separately, so that the structure may become complicated and the manufacturing cost may increase. As the result, it may be difficult to make the products compact.